View ML9040A-BXXWA_1280505.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PEDL9040A-03 Semiconductor
Semiconductor ML9040A-Axx/-Bxx
SEGMENT DRIVER
Pr PEDL9040A-03 el im i ThisML9040A-Axx/-Bxx nar version: Oct. 2000 y Previous version: Sep. 2000
DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT
GENERAL DESCRIPTION
The ML9040A-Axx/-Bxx is a dot matrix LCD controller which is fabricated in low power CMOS silicon gate technology. Character display on the dot matrix character type LCD can be controlled in combination with a 4-bit or 8-bit microcontroller. This LSI consists of 16-dot COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM, character generator ROM and control circuit. The ML9040A-Axx/-Bxx has the character generator ROM that can be programmed by custom mask. The ML9040A-A01/-B01 is a standard version having 160 characters with lowercase (5 x 7 dots), and 32 characters with uppercase (5 x 10 dots) in this ROM.
FEATURES
* Easy interface with an 8-bit or 4-bit microcontroller. * Dot matrix LCD controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots). * Automatic power ON reset. * COMMON signal drivers (16) and SEGMENT signal drivers (40). * Can control up to 80 characters when used in combination with MSM5259. * Character generator ROM for 160 characters with lowercase (5 x 7 dots) and 32 characters with uppercase (5 x 10 dots). * Character patterns are programmable by character generator RAM. (Lowercase: 5 x 8 dots, 8 patterns, uppercase: 5 x 11 dots, 4 patterns). * Built-in oscillation circuit to connect with external resistor or ceralock. * 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2 lines; 5 x 7 dots + cursor), selectable. * Clear display even at 1/5 bias, 3.0V LCD driving voltage. * LCD driving waveform ML9040A-Axx: A mode ML9040A-Bxx: B mode * Package options: 80-pin plastic QFP(QFP80-P-1420-0.80-BK)(Product name: ML9040A-Axx/-BxxGA) Al pad chip (Product name: ML9040A-Axx/-BxxWA) xx indicates code number. 01 indicates standard code number.
1/49
Semiconductor
BLOCK DIAGRAM
VDD GND
L CP DF Timing generation circuit 7 Cursor blink control 16-bit shift register 16 Common signal driver 16 COM1~16
OSC1 OSC2
E RS R/W
8 8 5 Parallel/ serial conversion 7 5 8 8 Data register (DR) 8 40
40-bit shift register
Instruction register (IR)
Instruction decoder (ID)
DB0 - DB3
4
Input/ output buffer
Character generator RAM (CG RAM)
DB4 - DB7
4
Character generator ROM (CG RAM)
40-bit latch
Busy flag (BF)
40 Seg- 40 ment signal SEG1~40 driver 8
V1 V2 V3 V4 V5
Address counter (ADC) 7
Display data RAM (DD RAM)
DO
PEDL9040A-03
ML9040A-Axx/-Bxx
2/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
INPUT AND OUTPUT CONFIGURATION
VDD
VDD
P N
Applicable to pin E.
Applicable to pins R/W and RS.
VDD
VDD
P
VDD
N
VDD
P
P N
Applicable to pins DO, CP, L, and DF.
N
Applicable to pins DB0 - DB7.
3/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
PIN CONFIGURATION (TOP VIEW)
ML9040A-Axx/-Bxx GA

80 77 76 75 74 73 72 71 70 79 78
69
68
67
66
65
SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1
1
2 3 4 5 6 7 8 9
10 11 12 13 14 15
16
17 18 19 20 21 22 23 24
SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2
25
33
39
26
27
28
29
30
31
32
34
35
36
37
OSC2
V1 V2 V3 V4 V5 L CP VDD DF DO RS R/W E DB0 DB1
80-Pin Plastic QFP
38
40
4/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
PIN DESCRIPTIONS
Symbol R/W RS E DB0 - DB7 OSC1, OSC2 COM1 - COM16 SEG1 - SEG40 DO CP L DF VDD GND V1, V2, V3, V4, V5 TEST Read/write selection input pin. "H" : Read, and "L" : Write Register selection input pin. "H" : Data register, and "L" : Instruction register Input pin for data input/output with CPU and for instruction register activation. Input/output pins for data send/receive with CPU Clock oscillating pins required for internal operation upon receipt of the LCD drive signal and CPU instruction. LCD COMMON signal output pins. LCD SEGMENT signal output pins. Output pin to be connected to MSM5259 to expand the number of characters to be displayed. Clock output pin used when DO pin data output shifts inside of MSM5259. Clock output pin for the serially transferred data to be latched to MSM5259. The alternating current signal (Display Frequency) output pin. Power supply pin. Ground pin. Bias voltage input pins to drive the LCD. This is the pin for testing the IC chip. Leave this pin open during normal use. *This pin is available only for Al pad chip. Description
5/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage LCD Driving Voltage Symbol VDD V1, V2, V3 V4, V5 VI PD TSTG Condition Ta = 25C Ta = 25C Rating -0.3 to + 7.0 VDD - 8.0 to VDD + 0.3 -0.3 to VDD + 0.3 500 -55 to + 150 Unit V V Applicable pin VDD, GND V1, V2, V3 V4, V5 R/W, RS, E, Input Voltage Power Dissipation Storage Temperature Ta = 25C -- -- V mW C DB0 - DB7 OSC1 -- --
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Data Holding Voltage*1 LCD Driving Voltage*2 Operating Temperature Symbol VDD VHOLD VLCD Top Condition -- -- 1/4 bias, VDD-V5*3 1/5 bias, VDD-V5 --
*4
Range 4.5 to 5.5 3.0 to 5.5 3.0 to 6.0 3.0 to 6.0 -20 to + 75
Unit V V V V C
Applicable pin VDD, GND VDD, GND VDD, V5 --
*1 Voltage to assure Rf oscillation and register data retention. *2 Voltage between VDD and V5. *3 Voltages applicable to V1, V2, V3 and V4 are as follows. V1 = VDD - 1/4 (VDD - V5) V2 = V3 = VDD - 1/2 (VDD - V5) V4 = VDD - 3/4 (VDD - V5) *4 V1 = VDD - 1/5 (VDD - V5) V2 = VDD - 2/5 (VDD - V5) V3 = VDD - 3/5 (VDD - V5) V4 = VDD - 4/5 (VDD - V5)
6/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Input Voltage "L" Input Voltage "H" Output Voltage "L" Output Voltage "H" Output Voltage "L" Output Voltage Driver ON Resistor (COM pins) Driver ON Resistor (SEG pins)
Input Leakage Current
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Condition -- -- -- -- IO = -0.205mA IO = 1.2mA IO = -40mA IO = 40mA IO = 50mA, VLCD = 4V IO = 50mA, VLCD = 4V VI = VSS VI = VDD VDD = 5.0V VI = VSS Min. 2.2 -0.3 VDD-1.0 -0.3 2.4 -- 0.9VDD -- -- -- -- -- -50 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -125 Max. VDD 0.6 VDD 1.0 -- 0.4 -- 0.1VDD 20 30 -1 1 -250 Unit V V V V V V V V kW kW mA mA mA R/W, RS -- -- 2 mA DB0 - DB7 Applicable pin RS, E, DB0 - DB7 DB0 - DB7, RS, E, R/W OSC1, R/W OSC1 DB0 - DB7 DO, CP, L, DF, OSC2 COM1 - COM16 SEG1 - SEG40 E
Symbol VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG
IIL
Input Current
IIL2
VI = VDD, excluding current flowing over pullup resistor and output drive MOS VDD = 5.0V, resistor oscillation or external clock input via OSC1.
Supply Current (1)
IDD1
fOSC = 270kHz. E is in "L" level. Other inputs are open. Output pins are all no load. VDD = 5.0V, ceramic oscillation, fOSC = 250kHz. *1
--
0.35
0.6
mA
VDD
Supply Current (2)
IDD2
E is in "L" level. Other pins are open. Output pins are all no load. *1 1/5 bias 1/4 bias
--
0.55
0.8
mA
VDD
LCD Driving Bias Input Voltage Schmitt voltage width Built-in reset detection voltage
VLCD1 VLCD2 VSUM VRES
VDD-V5 ------ ------
*6
3.0 3.0 0.6 --
-- -- 0.7 --
6.0 6.0 0.8 3.0
V V V
VDD, V1, V2, V3, V4, V5 E VDD
7/49
PEDL9040A-03 Semiconductor AC Characteristics
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Parameter Rf Clock Oscillation Frequency Clock Input Frequency Input Clock Duty Input Clock Rise Time Input Clock Fall Time Ceramic Unit Oscillation Frequency fOSC Symbol fOSC1 fIN fDUTY tr tf Rf = 510kW, C1 = C2 = 200 pF, Rd = 30kW, and Ceralock CSB250A. *5 245 250 255 kHz OSC1 OSC2 Condition Rf = 91kW 2% *2 OSC2 is open. Input from OSC1 *3 *4 *4 Min. 190 125 45 -- -- Typ. 270 250 50 -- -- Max. 350 350 55 0.2 0.2 Unit kHz kHz % ms ms Applicable pin OSC1 OSC2 OSC1 OSC1 OSC1 OSC1
ML9040A-Axx/-Bxx
*1 Applicable to the current that flows in pin VDD when power is input as follows: VDD = 5V, GND = 0V, V1 = 3.8V, V2 = 2.6V, V3 = 1.4V, V4 = 0.2V, and V5 = -1V.
*2 OSC1 Rf OSC2 Rf=91kW2% Minimum wiring is required between OSC1 and Rf and between OSC2 and Rf.
8/49
PEDL9040A-03 Semiconductor
*3 Applied to pulse input via OSC1.
ML9040A-Axx/-Bxx
tHW
tLW
fIN waveform
0.5VDD
0.5VDD
0.5VDD
fDUTY = tHW/ (tHW + tLW) x 100(%) *4 Applied to pulse input via OSC1. VDD-1.0V fIN waveform 1.0V tr tf C1 OSC1 Rf OSC2 Rd C2 Ceralock VDD-1.0V 1.0V
*5
Ceralock : CSB250A (mfd. by MURATA MFG.Co.) Rf : 510kW 5% Rd : 30kW 5% C1 : 200pF 10% C2 : 200pF 10% Please contact us when using this circuit.
*6 Input the voltage listed in the table below to V1 - V5:
N (LCD lines) 1-line mode Pin V1 V2 V3 V4 V5 VDD - VLCD 4 V VDD - LCD 2 V VDD - LCD 2 3VLCD VDD - 4 VDD - VLCD VLCD 5 2VLCD VDD - 5 VDD - 3VLCD 5 4VLCD VDD - 5 VDD - VDD - VLCD 2-line mode
VLCD is an LCD driving voltage. (For "N" (number of LCD lines), refer to the initial set of the instruction code.)
9/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Switching Characteristics
* Timing for input from the CPU
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Parameter R/W and RS setup time E "H" pulse width R/W and RS hold time E rise time E fall time E "L" pulse width E cycle time DB0 to DB7 input data setup time DB0 to DB7 input data hold time Symbol tB tW tA tr tf tL tC tI tH Min. 140 280 10 -- -- 280 667 180 10 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 100 100 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
R/W
VIL1
VIL1
RS
VIH1
VIL1 tB VIL1 tr tI
VIH1 VIH1
VIH1
VIL1 tW
VIH1
tA tL
E
VIL1 tH
VIH1
VIL1
tf
DB0 - DB7
VIL1 Input data
VIL1 tC
10/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
* Timing for output to the CPU
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Parameter R/W and RS setup time E "H" pulse width R/W and RS hold time E rise time E fall time E "L" pulse width E cycle time DB0 to DB7 data output delay time DB0 to DB7 data output hold time Symbol tB tW tA tr tf tL tC tD tO Min. 140 280 10 -- -- 280 667 -- 20 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 100 100 -- -- 220 -- Unit ns ns ns ns ns ns ns ns ns
R/W
VIH2
VIH2
RS
VIH1
VIL1
VIH1
VIL1
tB VIH1 tD DB0-DB7
tW VIH1 tf
tA tL
E
VIL1
VIL1
VIL1
tr
tO
VOH1 VOL1 Output data VOH1 VOL1
tC
11/49
PEDL9040A-03 Semiconductor * Timing for output to MSM5259
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Parameter CP "H" pulse width CP "L" pulse width DO setup time DO holding time "L" clock set-up time "L" clock hold time "L" "H" pulse width DF delay time Symbol tHW1 tLW tS tDH tSU tHO tHW2 tM Min. 800 800 300 300 500 100 800 -1000 Typ. -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 1000 Unit ns ns ns ns ns ns ns ns
ML9040A-Axx/-Bxx
DO tHW1
VOH2 VOH2
VOH2 VOL2
VOH2 VOL2
tLW
VOL2 VOL2
ts
VOH2 VOL2
tDH
VOH2 tSU VOH2 VOH2 tHW2 tM VOH2 tHO
CP
L
VOL2
DF
12/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
FUNCTIONAL DESCRIPTION Instruction Register (IR) and Data Register (DR)
These two registers are selected by the REGISTER SELECTION (RS) pin. The DR is selected when the "H" level is input to the RS pin and IR is selected when the "L" level is input. The IR is used to store the address of the display data RAM (DD RAM) or character generator RAM (CG RAM) and instruction code. The IR can be written, but not be read by the microcomputer (CPU). The DR is used to write and read the data to and from the DD RAM or CG RAM. The data written to DR by the CPU is automatically written to the DD RAM or CG RAM as an internal operation. When an address code is written to IR, the data (of the specified address) is automatically transferred from the DD RAM or CG RAM to the DR. Next, when the CPU reads the DR, it is possible to verify DD RAM or CG RAM data from the DR data. After the writing of DR by the CPU, the next adress in the DD RAM or CG RAM is selected to be ready for the next CPU writing. Likewise, after the reading out of DR by the CPU, DD RAM or CG RAM data is read out by the DR to be ready for the next CPU reading. Write/read to and from both registers is carried out by the READ/WRITE (R/W) pin. Table 1 RS and R/W pins functions
R/W L H L H RS L L H H IR write Read of busy flag (BF) and address counter (ADC) DR write DR read Function
Busy Flag (BF) When the busy flag is at "H", it indicates that the ML9040A-Axx/-Bxx is engaged in internal operation. When the busy flag is at "H", any new instruction is ignored. When R/W = "H" and RS = "L", the busy flag is output from DB7. New instruction should be input when busy flag is "L" level. When the busy flag is at "H", the output code of the address counter (ADC) is undefined. Address Counter (ADC) The address counter (ADC) allocates the address for the DD RAM and CG RAM write/ read and also for the cursor display. When the instruction code for a DD RAM address or CG RAM address setting is input to IR, after deciding whether it is DD RAM or CG RAM, the address code is transferred from IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the ADC is incremented (decremented) by 1 internally. The data of the ADC is output to DB0 - DB6 on the conditions that R/W = "H", RS = "L", and BF = "L".
13/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG ROM. It is designed so that the internal operation caused by accessing from the CPU will not interfer e with the internal operation caused by LCD driving. Consequently, when data is written from the CPU to DD RAM, flickering does not occur in a display area other than the display area where the data is written. In addition, this circuit generates the transfer signal to MSM5259 for display character expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2). DD RAM address corresponds to the display position of the LCD. The correspondence between the two is described in the following. DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
DB6 ADC MSB Hexadecimal notation (Example) When DD RAM address is 2A L H 2 L H Hexadecimal notation L A H
DB0 LSB
L
(1) Corresponden ce between address and display position in the 1-line display mode
First digit 00 MSB 2 01 3 02 4 03 5 04 79 4E 80 4F LSB Display position DD RAM address (hex.)
(2) When the ML9040A-Axx/-Bxx alone is used, up to 8 characters can be displayed from the first to eighth digit.
First digit 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07
When the display is shifted by instruction, the correspondence between the LCD display position and the DD RAM address changes as shown below:
(Display shifted to right) (Display shifted to left) First digit 4F First digit 01 2 00 3 01 4 02 5 03 6 04 7 05 8 06
2 02
3 03
4 04
5 05
6 06
7 07
8 08
14/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
(3) When the ML9040A-Axx/-Bxx is used with one MSM5259, up to 16 characters can be displayed from the first to sixteenth digit as shown below:
First digit 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B 13 0C 14 0D 15 0E 16 0F
ML9040A-Axx/-Bxx display
MSM5259 display
When the display is shifted by instruction, the correspondence between the LCD display and the DD RAM address changes as shown below:
First digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E ML9040A-Axx/-Bxx display (Display shifted to left) MSM5259 display
(Display shifted to right)
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
(4) Since the ML9040A-Axx/-Bxx has a DD RAM capacity of up to 80 characters, up to 9 MSM5259 devices can be connected to ML9040A-Axx/-Bxx so that 80 characters can be displayed.
First digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 ML9040A-Axx/-Bxx display MSM5259 (1) display MSM5259 (2) - (8) display 73 74 75 76 77 78 79 80 48 49 4A 4B 4C 4D 4E 4F MSM5259 (9) display
15/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
(5) Correspondence between address and display position in the 2-line display mode
First digit First line Second line 00 40 2 01 41 3 02 42 4 03 43 5 04 44 39 26 66 40 27 67 Display position DD RAM address (hex.)
(Note) The last address of the first line is not consecutive to the head address of the second line. (6) When ML9040A-Axx/-Bxx alone is used, up to 16 characters (8 characters x 2 lines) can be displayed from the first to eighth digit.
First digit 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47
First line Second line
When the display is shifted by instruction, the correspondence between the LCD display position and the DD RAM address changes as shown below:
First digit 27 67 First digit (Display shifted to left) First line Second line 01 41 2 00 40 3 01 41 4 02 42 5 03 43 6 04 44 7 05 45 8 06 46
(Display shifted to right)
First line Second line
2 02 42
3 03 43
4 04 44
5 05 45
6 06 46
7 07 47
8 08 48
(7) When the ML9040A-Axx/-Bxx is used with one MSM5259, up to 32 characters (16 characters x 2 lines) can be displayed from the first to the sixteenth digit.
First digit 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A 12 0B 4B 13 0C 4C 14 0D 4D 15 0E 4E 16 0F 4F
First line Second line
ML9040A-Axx/-Bxx display
MSM5259 display
16/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
When the display is shifted by instruction, the correspondence between the LCD display position and the DD RAM address changes as shown below:
(Display shifted to right) First digit First line Second line 27 67 2 00 40 3 01 41 4 02 42 5 03 43 6 04 44 7 05 45 8 06 46 9 07 47 10 08 48 11 09 49 12 0A 4A 13 0B 4B 14 0C 4C 15 0D 4D 16 0E 4E
ML9040A-Axx/-Bxx display (Display shifted to left) First digit 2 01 02 41 42 3 03 43 4 04 44 5 05 45 6 06 46 7 07 47 8 08 48 9 09 49 10 0A 4A
MSM5259 display
First line Second line
11 0B 4B
12 0C 4C
13 0D 4D
14 0E 4E
15 0F 4F
16 10 50
ML9040A-Axx/-Bxx display
MSM5259 display
(8)Since the ML9040A-Axx/-Bxx has a DD RAM capacity of up to 80 characters, up to 4 MSM5259 devices can be connected to the ML9040A-Axx/-Bxx in the 2-line display mode.
First digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 First line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 Second line 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 ML9040A-Axx/-Bxx display MSM5259 (1) display 33 34 35 36 37 38 39 40 20 21 22 23 24 25 26 27 60 61 62 63 64 65 66 67
MSM5259 MSM5259 (4) display (2) - (3) display
Character Generator ROM (CG ROM)
The CG ROM is used to generate 5 x 7 dots (160 kinds) or 5 x 10 dots (32 kinds) character patterns from an 8-bit DD RAM character code signal. The correspondence between 8-bit character codes and character patterns of standard code 01 is shown in Table 2. When the 8-bit character code of the CG ROM is written to the DD RAM, the character pattern of the CG ROM corresponding to the code is displayed on the LCD display position corresponding to the DD RAM address.
17/49
Semiconductor
Lower 4 bits
Upper 4 bits
Table 2 Relationship Between Character Codes and Characters (Character Patterns) of ML9040A-A01/-B01
MSB 0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
0000 LSB 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
CG RAM (1) (2) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) - . / ( ) * + # $ % & !
0 1 2 3 4 5 6 7 8 9 : ; < = > ?
@ A B C D E F G H I J K L M N O
P Q R S T U V W X Y Z [ ] ^ _
/ a b c d e f n h i j k l m n o
p q r s t u v w x y z { U } AE
a a b e m s r g -1
j
R q Q * W u S p X
x n o /
ML9040A-Axx/-Bxx
PEDL9040A-03
18/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Character Generator RAM (CG RAM)
The CG RAM is used to display user's original character patterns other than character patterns in the CG ROM. The CG RAM has a capacity (64 bytes = 512 bits) of writing 8 kinds of characters for 5 x 7 dots and 4 kinds of characters for 5 x 10 dots. When displaying character patterns stored in the CG RAM, write 8-bit character codes (00 to 07 or 08 to 0F; hex.) on the left side as shown in Table 2. Then it is possible to output the character pattern to the LCD display position corresponding to the DD RAM address. The following explains how to write and read character patterns to and from the CG RAM. (1) When the character pattern is 5 x 7 dots (see Table 3-1). * A method of writing character pattern to the CG RAM by CPU: Three bits of CG RAM addresses 0-2 correspond to the line position of the character pattern. First, set increment or decrement by the CPU, and then input the CG RAM address. After this, write character patterns to the CG RAM through DB0 - DB7 line by line. DB0 to DB7 correspond to CG RAM data 0-7 in Table 3-1. It is displayed when "H" is set as input data and is not displayed when "L" is set as input data. Since the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. The line, in which the CG RAM addresses 0-2 are all "H" ("7" in hexadecimal notation), is the cursor position. It is ORed with the cursor at the cursor position and displayed to LCD. For this reason, it is necessary to set all input data that become cursor positions to "L". Although CG RAM data 0-4 bits are output to the LCD as display data, CG RAM data bits 5-7 are not output. The latter can be written and read to and from the RAM, it is therefore allowed to be used as data RAM. * A method of displaying the CG RAM character pattern to the LCD: The CG RAM is selected when upper 4 bits of the character codes are all "L". As character code bit 3 is invalid, the display of "0" in Table 3-1, is selected by character code "00" (hex.) or "08" (hex.). When the 8-bit character code of the CG RAM is written to the DD RAM, the character pattern of the CG RAM is displayed on the LCD display position corresponding to the DD RAM address. (DD RAM data, bits 0-2 correspond to CG RAM address, bits 3-5.)
19/49
PEDL9040A-03 Semiconductor (2) When character pattern is 5 x 10 dots (see Table 3-2). * A method of writing character pattern into the CG RAM by the CPU: Four bits of CG RAM address, bits 0-3, correspond to the line position of the character pattern. First, set increment or decrement with the CPU, and then input the address of the CG RAM. After this, write the character pattern code into the CG RAM, line by line from DB0DB7. DB0 to DB7 correspond to CG RAM data, bits 0-7, in Table 3-2. It is displayed when "H" is set as input data, while it is not displayed when "L" is set as input data. As the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. The line, the CGRAM addresses 0-3 of which are "A" in hexadecimal notation, is the cursor position. The CGRAM data is 0Red with the cursor at the cursor position and displayed to LCD. For this reason, it is necessary to set all input data that become cursor positions to "L". When the CG RAM data, bits 0-4, and CG RAM addresses, bits 0-3, are "0" to "A", they are displayed on the LCD as the display data. When the CG RAM data, bits of 5-7, and CG RAM, bit data is 0-4 and CG RAM address data is "B" to "F", it is not output to the LCD. But in this case, CG RAM can be used as RAM and it can be written into/read out. So, it can be used as the data RAM. * A method of displaying the CG RAM character pattern to the LCD: The CG RAM is selected when 4-upper order bits of the character code are all "L". As character code bits 0 and 3 are invalid, the display of "m" is selected by character codes "00", "01", "08", and "09" (hex.) as in Table 3-2. When the CG RAM character code is written to the DD RAM, the CG RAM character pattern is displayed on the LCD display position corresponding to the DD RAM address. (DD RAM data bits 1 and 2 correspond to CG RAM address bits 4 and 5.) ML9040A-Axx/-Bxx
20/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Table 3-1 Relationship between CG RAM data (character pattern), CG RAM address and DD RAM data when the character pattern is 5 x 7 dots. The example below indicates "OKI".
CG RAM data
(character pattern) 7 6 MSB X X 5 X 4 L H H H H H L L H H H H H H H L L L L L L L L L 3 H L L L L L H L L L L H L L L L H L L L L L H L 2 H L L L L L H L L L H L H L L L H H H H H H H L 1 H L L L L L H L L H L L L H L L H L L L L L H L 0 LSB L H H H H H L L H L L L L L H L L L L L L L L L 7 6 MSB
CG RAM address
54 MSB L L 3 L 2 L L L L H H H H L L L L H H H H L L L L H H H H 1 L L H H L L H H L L H H L L H H L L H H L L H H 0 LSB L H L H L H L H L H L H L H L H L H L H L H L H
DD RAM data
(character code) 5 4 3 2 1 0 LSB
L
L
L
L
X
L
L
L
L
L
H
X
X
X
L
L
L
L
X
L
L
H
H
H
H
X
X
X
L
L
L
L
X
H
H
H
X : Don't Care
21/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Table 3-2 Relationship between CG RAM data (character pattern), CG RAM address and DD RAM data when the character pattern is 5 x 10 dots. The examples below indicate m, g and .
CG RAM data
(character pattern) 7 6 MSB X X 5 X 4 L H H H H H H H H L L X 3 L L L L L H L L L L L X 2 L L L L L H L L L L L X 10 LSB L L L L H L L L L L L X L H H H H H L L L L L X 7 6 MSB
CG RAM address
54 MSB L L 3 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H 2 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H 10 LSB L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H
L
H
X
X
X
L L L L L L L L H H H H H H H H
L L L L H H H H L L L L H H H H
L L H H L L H H L L H H L L H H
L H L H L H L H L H L H L H L H
X
X
X
X : Don't Care
W
DD RAM data
(character code) 5 4 3 2 10 LSB
L
L
L
L
X
L
L
X
L L L H H H L L L L L X
L L H L L L H L L H L X
L L H L L L H L L H L X
L L H L L L H L L H L X
L L H H H H H H H L L X
L
L
L
L
X
L
H
X
L L H L H H L L L L L X
L L H H L L H L L L L X
L L L L L L H L L L L X
L L H H L L H L L L L X
L L H L H H L L L L L X
L
L
L
L
X
H
H
X
22/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Cursor/Blink Control Circuit
This is a circuit that generates the LCD cursor and blink. This circuit is under the control of the CPU program. The display of the cursor and blink on the LCD is made at a position corresponding to the DD RAM address that is set in the ADC. The figure below shows an example of the cursor/blink position when the value of ADC is set to "07" (hex.).
DB6 ADC L L 0 First digit In 1-line display mode 00 L L H 7 H DB0 H
2 01
3 02
4 05
5 04
6 05
7 06
8 07
9 08
79 4E
80 4F
Cursor and blink position First digit In 2-line display mode First line Second line 00 40
2 01 41
3 02 42
4 03 43
5 04 44
6 05 45
7 06 46
8 07 47
9 08 48
39 26 66
40 27 67
Cursor and blink position
(Note) The cursor and blink are displayed even when the CG RAM address is set in the ADC. For this reason, it is necessary to inhibit the cursor and blink display while the CG RAM address is set in the ADC.
LCD Display Circuit (COM1 to COM16, SEG1 to SEG40, L, CP, DO, and DF)
As the ML9040A-Axx/-Bxx provides the COM signal outputs (16 outputs) and the SEG signal outputs (40 outputs), it can display 8 characters (1-line display) or 16 characters (2line display) as a unit. SEG1 to SEG40 are used to display 8-digit display on the LCD. To expand the display, an MSM5259 is used. The MSM5259, 40-dot segment driver, is used for expansion of the SEG signal output. Interface with the MSM5259 is made through data output pin (DO), clock output pin (CP), latch output pin (L), and display frequency pin (DF). The character pattern data is serially transferred to MSM5259 through DO and CP. When the data of 72 characters 360-bit (= 5bit/ch. x 72 ch. = 1-line display) or 32 characters 160-bit (5-bit/ch. x 32 ch. = 2-line display) is output, the latch pulse is also output through pin L. By this latch pulse, the data transferred serially to MSM5259 is latched to be used as display data. The display frequency signal (DF) required when LCD is displayed is also output from DF pin synchronously with this latch pulse.
23/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Built-in Reset Circuit
The ML9040A-Axx/-Bxx is automatically initialized when the power is turned on. During initialization, the busy flag (BF) holds "H" and does not accept instructions (other than the busy flag read). The busy flag holds "H" for 15 ms after VDD reaches 4.5V or more. During initialization, the ML9040A-Axx/-Bxx executes the follwing instructions: * * * * * * * * * Display clear Data length of interface with CPU: 8 bits (8B/4B = "H") LCD: 1-line display (N = "L") Character font: 5 x 7 dots (F = "L") ADC: Increment (I/D = "H") No display shift (SH = "L") Display: Off (DI = "L") Cursor: Off (C = "L") No blink (B = "L")
It is required to satisfy the following power supply conditions.
4.5V
0.2V VDD tON
0.2V
0.2V
tOFF
0.1ms tON 100ms
1ms tOFF
Fig. 1. Power ON/OFF Waveform
24/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Data Bus Connected with CPU
The data bus connected with CPU is available either once for 8 bits or twice for 4 bits. This allows the ML9040A-Axx/-Bxx to be interfaced with either an 8-bit or 4-bit CPU. (1) When the interface data bus is 8 bits Data bus DB0 to DB7 (8 lines) are all used and data input/output is carried out in one step. (2) When the interface data bus is 4 bits The 8-bit data input/output is carried out in two steps by using only high-order 4 bits of data bus DB4 to DB7 (4 lines) The first time data input/output is made for 4-high order bits (DB4 to DB7) and the second time data input/output is made for low-order 4 bits (DB0 to DB3). Even when the data input/output can be completed through high-order 4 bits, be sure to make another input/output of low-order 4 bits. (Example: Busy flag Read). Since the data input/output is carried out in two steps as one execution, no normal data transfer is executed from the next input/output if accessed only once.
25/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
RS
R/W
E
Busy (internal operation)
IR7 DB7 DB6 IR6 Busy
No Busy
DR7
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
DB0
IR0
ADC0
DR0
Instruction register(IR) write
Busy flag(BF)and address counter(ADC)read
Data register (DR)write
Fig. 2 8-Bit Data Transfer
26/49
Semiconductor
RS
R/W
E
Busy(internal operation)
DB7 IR7 IR3 Busy DB6 IR6 IR2
No Busy
ADC3
DR7
DR3
ADC6
ADC2
DR6
DR2
DB5
IR5
IR1
ADC5
ADC1
DR5
DR1
DB4
IR4
IR0
ADC4
ADC0
DR4
DR0
Instruction register (IR)write
Busy flag(BF)and address counter(ADC)read
Data register (DR)write
ML9040A-Axx/-Bxx
PEDL9040A-03
Fig. 3 4-Bit Data Transfer
27/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Instruction Code
The instruction code is defined as the signal through which the ML9040A-Axx/-Bxx is accessed by the CPU. The ML9040A-Axx/-Bxx begins operation upon receipt of the instruction code input. As the internal processing operation of ML9040A-Axx/-Bxx starts in a timing that does not affect the LCD display, the busy status continues for longer than the CPU cycle time. Under the busy status (when the busy flag is set to "H"), the ML9040A-Axx/-Bxx does not execute any instructions other than the busy flag read. Therefore, the CPU has to verify that the busy flag is set to "L" prior to the input of the instruction code. (1) Display clear:
R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L L L L L H
Instruction code
When this instruction is executed, the LCD display is cleared. I/D in the entry mode setting is set to "H" (increment). SH does not change. When the cursor and blink are in display, the blinking position moves to the left end of the LCD (the left end of the first line in the 2-line display mode). (Note) All DD RAM data goes to "20" (hex.), while the address counter (ADC) goes to "00" (hex.). The execution time is 1.53 ms (max.), when the OSC oscillation frequency is 270 kHz.
(2) Cursor home
Instruction code R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L L L L H X
X : Don't Care
When this instruction is executed while the cursor and blink are being displayed, the blinking position moves to the left end of the LCD (to the left end of the first line in the 2line display mode). While the display is in shift, the display returns to its original position before shifting. (Note) The address counter (ADC) goes to "00" (hex.). The execution time is 1.53 ms (max.), when the OSC oscillation frequency is 270 kHz.
28/49
PEDL9040A-03 Semiconductor (3) Entry mode setting
R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L L L H I/D SH
ML9040A-Axx/-Bxx
Instruction code
1 When the I/D is set, the 8-bit character code is written or read to and from the DD RAM, the cursor and blink shift to the right by 1 character position (I/D = "H"; increment) or to the left by 1 character position (I/D = "L"; decrement). The address counter is incremented (I/D = "H") or decremented (I/D = "L") by 1 at this time. Even after the character pattern code is written or read to and from the CG RAM, the address counter (ADC) is incremented (I/D = "H") or decremented (I/D = "L") by 1. 2 When SH = "H" is set, the character code is written to the DD RAM. Then the cursor and blink stop and the entire display shifts to the left (I/D = "H") or to the right (I/ D = "L") by 1 character position. When the character is read from the DD RAM during SH = "H", or when the character pattern data is written or read to or from the CG RAM during SH = "H", the entire display does not shift, but normal write/read is performed (the entire display does not shift, but the cursor and blink shift to the right (I/D = "H") or to the left (I/D = "L") by 1 character position. When SH = "L" is set, the display does not shift, but normal write/read is performed. The execution time when the OSC oscillation frequency is 270 kHz is 37 ms.
(4) Display mode setting
R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L L H DI C B
Instruction code
1 The DI bit controls whether the character pattern is displayed or not displayed. When DI is "H", this bit makes the LCD display the character pattern. When DI is "L", the LCD character pattern is not displayed. The cursor and blink are also cancelled at this time. (Note) Unlike the display clear, the character code is not rewritten at all. 2 The cursor is not displayed when C = "L" and is displayed when DI = "H" and C = "H". 3 The blink is cancelled when B = "L" and is executed when DI = "H" and B = "H". In the blink mode, all dots (including the cursor) and displaying character pattern and cursor are displayed alternately at 379.2 ms (in 5 x 7 dots character font) or 521.5 ms (in 5 x 10 dots character font) when the OSC oscillation frequency is 270 kHz. The execution time when the OSC oscillation frequency is 270 kHz is 37 ms.
29/49
PEDL9040A-03 Semiconductor (5) Cursor and display shift
Instruction code R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L H D/C R/L X X L L X : Don't Care
ML9040A-Axx/-Bxx
When D/C = "L" and R/L = "L", the cursor and blink positions are shifted to the left by 1 character position (ADC is decremented by 1). When D/C = L and R/L = "H", the cursor and blink positions are shifted to the right by 1 character position (ADC is incremented by 1). When D/C = "H" and R/L = "L", the entire display is shifted to the left by 1 character position. The cursor and blink positions are also shifted with the display (ADC remains unchanged). When D/C = "H" and R/L = "H", the entire display is shifted to the right by 1 character position. The cursor and blink positions are also shifted with the display (ADC remains unchanged). In the 2-line display mode, the cursor and blink positions are shifted from the first to the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.) in the first line. No such shifting is made in other cases. When shifting the entire display, the display pattern, cursor, and blink positions are in no case shifted between lines (from the first to the second line or vice versa). The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(6) Initial setting
Instruction code R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L H 8B/4B N F X X
X : Don't Care
1 When 8B/4B = "H", the data input/output to and from the CPU is carried out simultaneously by means of 8 bits DB7 to DB0. When 8B/4B = "L", the data input/output to and from the CPU is carried out in two steps through 4 bits of DB7 to DB4. 2 The 2-line display mode of the LCD is selected when N = "H", while the 1-line display mode is selected when N = "L". 3 The 5 x 7 dots character font is selected when F = "L", while the 5 x 10 dots character font is selected when F = "H" and N = "L". This initial setting has to be accessed prior to other instructions except for the busy flag read after the power is supplied to the ML9040A-Axx/-Bxx.
Number of display lines 1 line 1 line 2 lines 2 lines Character font 5 x 7 dots 5 x 10 dots 5 x 7 dots 5 x 7 dots Duty ratio 1/8 1/11 1/16 1/16 Number of biases 4 4 5 5 Number of COMMOM signals 8 11 16 16
N L L H H
F L H L H
30/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Generate biases externally and input them to VDD, V1, V2, V3, V4, and V5. When the number of biases is 4, input the same potential to V2 and V3. The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(7) CG RAM address setting
R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L H C5 C4 C3 C2 C1 C0
Instruction code
When CG RAM addresses, bits C5 to C0 (binary), are set, the CG RAM is specified, until the DD RAM address is set. Write/read of the character pattern to and from the CPU begins with addresses, bits C5 to C0, starting from CG RAM selection. The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(8) DD RAM address setting
Instruction code R/W RS L L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 H D6 D5 D4 D3 D2 D1 D0
When the DD RAM addresses D6 to D0 (binary) are selected, the DD RAM is specified until the DD RAM address is set. Write/read of the character code to and from the CPU begins with addresses D6 to D0 starting from DD RAM selection. In the 1-line display mode (N = H), however, D6 to D0 (binary) must be set to one of the values among "00" to "4F" (hex.). Likewise, in the 2-line mode, D6 to D0 (binary) must be set to one of the values among "00" to "27" (hex.) or "40" to "67" (hex.). When any value other than the above is input, it is impossible to make a normal write/ read of character codes to and from the DD RAM. The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(9) DD RAM and CG RAM data write
Instruction code R/W RS L H DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E7 E6 E5 E4 E3 E2 E1 E0
When E7 to E0 (binary) codes are written to the DD RAM or CG RAM, the cursor and display move as described in "(5) Cursor and display shift". The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
31/49
PEDL9040A-03 Semiconductor (10) Busy flag and address counter read (Execution time is 1 ms.)
R/W RS H L DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF O6 O5 O4 O3 O2 O1 O0
ML9040A-Axx/-Bxx
Instruction code
The busy flag (BF) is output by this instruction to indicate whether the ML9040A-Axx/ -Bxx is engaged in internal operations (BF = "H") or not (BF = "L"). When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF = "L" before inputting a new instruction. When BF = "L", a correct address counter value is output. The address counter value must match the DD RAM address or CG RAM address. The decision of whether it is a DD RAM address or CG RAM address is made by the address previously set. Since the address counter value when BF = "H" is sometimes incremented or decremented by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
Instruction code R/W RS H H DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P7 P6 P5 P4 P3 P2 P1 P0
Character codes (bits P7 to P0) are read from the DD RAM, while character patterns (P7 to P0) from the CG RAM. Selection of DD RAM or CG RAM is decided by the address previously set. After reading those data, the address counter (ADC) is incremented or decremented by 1 as set by the shift mode mentioned in item "(3) shift mode set". The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms. (Note) Conditions for the reading of correct data: 1 When the DD RAM address set or CG RAM address set is input before inputting this instruction. 2 When the cursor/display shift is input before inputting this instruction in case the character code is read. 3 Data after the second reading from RAM when read more than 2 times. Correct data is not output in any other case.
32/49
PEDL9040A-03 Semiconductor Interface with LCD and MSM5259 Display examples when setting the 5 x 7 dots character font 1-line mode, 5 x 10 dots character font 1-line mode, and 5 x 7 dots character font 2-line mode through instructions are shown in Figures 4, 5, and 6, respectively. When the 5 x 7 dots character font is set in the 1-line display mode, the COM signals COM9 to COM16 are output for extinguishing. Likewise, when the 5 x 10 dots character font (1-line is set), the COM signals COM12 to COM16 are output for display-off. The display example shows a combination of 16 characters (32 characters for the 2-line display mode) and the LCD. When the number of MSM5259s are increased according to the increase in the number of characters, it is possible to display a maximum of 80 characters. Besides, it is necessary to generate bias voltage required for LCD operation by splitting resistors outside the IC to input it to ML9040A-Axx/-Bxx and MSM5259. Examples of these bias voltages are shown in Figures 7, 8, 9, and 10. Basically, this can be done by dividing the voltage by the resistors as shown in Figures 7 and 8. If the value of resistor R is made larger to reduce system power consumption, the LCD operating margin decreases and the LCD driving waveform is distorted. To prevent this, a by-pass capacitor is serially connected to the resistor to lower voltage division impedance caused by the splitting of resistors as shown in Figures 9 and 10. As the values of R, VR, and C vary according to the LCD size used and VLCD (LCD drive voltage), these values have to be determined through actual experimentation in combination with the LCD. (Example set values: R = 3.3 to 10kW, VR = 10 to 30kW, and C = 0.0022 mF to 0.047 mF) Figure 17 shows an application circuit for the ML9040A-Axx/-Bxx and MSM5259 including a bias circuit. The bias voltage has to maintain the following potential relation: VDD > V1 > V2 V3 > V4 > V5 * In the case of 1-line 16 characters display (5 x 7 dots/font) ML9040A-Axx/-Bxx
COM1 LCD COM8
SEG1 ML9040A-Axx/-Bxx DF
SEG40 DO CP L
O1 DI1 CP LOAD MSM5259 DF
O40
DO20 DI21
Figure 4
33/49
PEDL9040A-03 Semiconductor * In the case of 16-character (1 line) display (5 x 10 dots/font) ML9040A-Axx/-Bxx
COM1
LCD
COM11
SEG1 ML9040A-Axx/-Bxx DF
SEG40 DO CP L
O1 DI1 CP LOAD MSM5259 DF DO20
O40
DI21
Figure 5
* In the case of 16-character (2 lines) display (5 x 7 dots/font)
COM1
COM7 COM8 COM9
LCD
COM15 COM16
SEG1
SEG40 DO CP DF L
O1 DI1 CP LOAD DF DO20 MSM5259
O40
ML9040A-Axx/-Bxx
DI21
Figure 6
34/49
PEDL9040A-03 Semiconductor * Bias voltage circuit (1-line display mode)
VDD R V1 V2 R VLCD
ML9040A-Axx/-Bxx * Bias voltage circuit (2-line display mode)
VDD R V1 R V2 VLCD
ML9040A-Axx/-Bxx
V3 V4 R V5 VR R
ML9040A-Axx/-Bxx
V3
R
R V4 VR V5
Figure 7
Figure 8
* Bias voltage circuit (1-line display mode)
* Bias voltage circuit (2-line display mode)
VDD
VDD R V1 V2 ML9040A-Axx/-Bxx V3 V4 R V5 C VR R C R C VLCD
ML9040A-Axx/-Bxx
R
C
C
V1 R V2 R V3 R V4 R C VR C VLCD C
C
C
V5 C
Figure 9
(VLCD : LCD driving voltage)
Figure 10
35/49
Semiconductor
* Application circuit
LCD
COM1-16 DO DO40 DO20 DI21 VDD VSS V2 V3 VEE DI21 DO20 DI1 CP LOAD DF VDD VSS V2 V3 VEE DI1 CP LOAD DF
SEG1-40
O1 - O40 MSM5259
O1 - O40 MSM5259 DO40
O1 - O40 MSM5259 DO40 DO20 DI21 VDD VSS V2 V3 VEE DI1 CP LOAD DF
Figure 11
CP L DF VDD GND V1 V2 V3 V4 V5 C C C C C C R +5V R R R R VR 0V
ML9040A-Axx/-Bxx
PEDL9040A-03
ML9040A-Axx/-Bxx
36/49
PEDL9040A-03 Semiconductor LCD Drive Waveforms Figures 12, 13 and 17 show the LCD driving waveforms consisting of COM signal, SEG signal, DF signal and L (latch pulse waveform) signal, in the duty of 1/8, 1/11 and 1/16 respectively. The relation between duty and frame frequency is described in the table below. ML9040A-Axx/-Bxx
Duty 1/8 1/11 1/16
Frame frequency 84.3 Hz 61.4 Hz 84.3 Hz
(Note) The OSC oscillation frequency is assumed to be 270 kHz.
37/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
8 COM1 VDD V1 V2,V3 V4 V5
1
2
3
4
5
6
7
8
1
2
1 frame
COM2
VDD V1 V2,V3 V4 V5
COM8
VDD V1 V2,V3 V4 V5
COM9
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5
Display-off waveform SEG V1 (Output V2,V3 example) V4
V5 VDD
Display-on waveform
DF L
Figure 12. LCD Driving Waveforms (A mode) at 1/8 Duty
38/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
11 COM1 VDD V1 V2,V3 V4 V5
1
2
3
4
5
6
7
8
9
10
11
1
2
1 frame
COM2
VDD V1 V2,V3 V4 V5
COM11
VDD V1 V2,V3 V4 V5
COM12
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5
Display-off waveform SEG (Output example)
VDD V1 V2,V3 V4 V5
Display-on waveform
DF L
Figure 13. LCD Driving Waveforms (A mode) at 1/11 Duty
39/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
16 COM1 VDD V1 V2 V3 V4 V5
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16
1
2
1 frame
COM2
VDD V1 V2 V3 V4 V5
COM16
VDD V1 V2 V3 V4 V5
Display-off waveform SEG (Output example)
VDD V1 V2 V3 V4 V5
Display-on waveform
DF L
Figure 14. LCD Driving Waveforms (A mode) at 1/16 Duty
40/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
78123456781234567812 COM1 VDD V1 V2,V3 V4 V5
1 frame
COM2
VDD V1 V2,V3 V4 V5
COM8
VDD V1 V2,V3 V4 V5
COM9
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5
SEG (Output example)
VDD V1 V2,V3 V4 V5
Display turning-off waveform
Display turning-on waveform
DF
L
Figure 15. LCD Driving Waveforms (B mode) at 1/8 Duty
41/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
1011 1 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 COM1 VDD V1 V2,V3 V4 V5
1 frame
COM2
VDD V1 V2,V3 V4 V5
COM11
VDD V1 V2,V3 V4 V5
COM12
VDD V1 V2,V3 V4 V5
COM16
VDD V1 V2,V3 V4 V5
SEG (Output example)
VDD V1 V2,V3 V4 V5
Display turning-off waveform
Display turning-on waveform
DF
L
Figure 16. LCD Driving Waveforms (B mode) at 1/11 Duty
42/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 COM1 VDD V1 V2 V3 V4 V5
1 frame
COM2
VDD V1 V2 V3 V4 V5
COM16
VDD V1 V2 V3 V4 V5
SEG (Output example)
VDD V1 V2 V3 V4 V5
Display turning-off waveform
Display turning-on waveform
DF
L
Figure 17. LCD Driving Waveforms (B mode) at 1/16 Duty
43/49
PEDL9040A-03 Semiconductor Initial Setting of Instruction (1) When data input/output to and from the CPU is carried out by 8 bits (DB0 to DB7): q w e r t y u i o !0 !1 !2 !3 !4 !5 !6 !7 Turn on the power. Wait for 15 ms or more after VDD has reached 4.5V or more. Set 8B by initial setting of instruction. Wait for 4.1 ms or more. Set 8B by initial setting of instruction. Wait for 100 ms or more. Set 8B by initial setting of instruction. Check the busy flag as No Busy. Set 8B. Set LCD line number (N) and character font (F). (After this, the LCD line number and character font cannot be changed.) Check No Busy. Clear the display by setting the display mode. Check No Busy. Clear the display. Check No Busy. Set the shift mode. Check No Busy. Initial setting completed. ML9040A-Axx/-Bxx
Example of Instruction Code for Steps e, t, and u.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L H H X X X X L L X : Don't Care
44/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
(2) When data input/output to and from the CPU is carried out by 4 bits (DB4 to DB7): q w e r t y u i o !0 !1 !2 !3 !4 !5 !6 !7 !8 !9 Turn on the power. Wait for 15 ms or more after VDD has reached 4.5V or more. Set 8B by initial setting of instruction. Wait for 4.1 ms or more. Set 8B by initial setting of instruction. Wait for 100 ms or more. Set 8B by initial setting of instruction. Check the busy flag as No Busy. Set 4B by initial setting of instruction. Wait for 100 ms or more. Set 4B, LCD line number (N) and character font (F) by initial setting of instruction. (After this, the LCD line number and character font cannot be changed.) Check No Busy. Clear the display by setting the display mode. Check No Busy. Clear the display. Check No Busy. Set the shift mode. Check No Busy. Initialization completed.
Example of Instruction Code for Steps e, t, and u.
R/W RS L L DB7 DB6 DB5 DB4 L L H H
Example of Instruction Code for Step o.
R/W RS L L DB7 DB6 DB5 DB4 L L H L
Example of Instruction Code for Step i.
RS1 RS0 R/W DB7 DB6 DB5 DB4 H L H BF Q6 Q5 Q4
Execute two-step accesses in 4 bits from Step !1 to Step !8.
45/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
PAD CONFIGURATION
Pad Layout Chip size: 2.94 x 4.32 mm Passivation film etched hole: 80 x 80 mm
57 Y 43
58
42
X
81
18 1
X(m) Y (m)
Pad Coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
17
Pad Name SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20
Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pad Name SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 TEST
X(m)
Y (m)
-1310 -1156 -1002 -848 -694 -540 -386 -233 -79 75 229 383 537 691 845 999 1153 1309 1311 1311
-1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1955 -1615 -1478
1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311 1311
-1342 -1206 -1070 -934 -797 -661 -525 -389 -253 -116 20 156 292 428 565 701 837 973 1109 1296
46/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
Pad Name GND OSC1 OSC2 V1 V2 V3 V4 V5 L CP VDD DF DO RS RW E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40
X(mm)
Y(mm)
1311 1311 1049 738 576 414 252 90 --347 --491 --610 --710 --810 --910 --1010 --1111 --1211 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311 --1311
1426 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1955 1783 1369 1184 1000 816 632 148 48 --52 --152 --253 --353 --453 --553 --653 --754 --854 --954 --1054 --1154 --1255 --1355 --1455
47/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 1.27 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
48/49
PEDL9040A-03 Semiconductor ML9040A-Axx/-Bxx
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
2.
3.
4.
5.
6.
7.
8.
9.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
49/49

▲Up To Search▲

Price & Availability of ML9040A-BXXWA

	To Download ML9040A-BXXWA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .